----------------------------------------------------------------------------------
-- INSTITUTION:    Xidian University
-- DESIGNER:       Yuan Xiaoguang & Ren Aifeng    
-- 
-- Create Date:    16:53:58 02-14-2016 
-- Design Name:    PWM_COUNTER 
-- Module Name:    PWM_COUNTER
-- Project Name:   PWM
-- Target Devices: EP3C16F484C6
-- Tool versions:  Quartus II 13.1
-- Design Lauguage:VHDL
-- Dependencies:   -
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: DE0 Board Input Freguency = 50 MHz
--                      Destiny Output  Freguency =  1 Hz
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity PWM_VALUE_SET is
	port(
		i_sys_clk: in STD_LOGIC;
		i_sys_rst: in STD_LOGIC;
	   i_ext_trig: in STD_LOGIC;	      --
		o_compare_set_value: out STD_LOGIC_VECTOR (7 downto 0)
	);
end entity PWM_VALUE_SET;

architecture behavior of PWM_VALUE_SET is
	signal r_ext_trig: STD_LOGIC;
	signal w_ext_trig: STD_LOGIC;
	signal r_compare_set_value: STD_LOGIC_VECTOR (7 downto 0);
begin
	process(i_sys_rst,i_sys_clk)	
		begin
			if (i_sys_rst = '1') then	
				r_ext_trig <='0';
				elsif (i_sys_clk'event AND i_sys_clk = '1') then	--当时钟是上升沿时，输出为1
				r_ext_trig <= i_ext_trig;             --赋值
			end if;
	end process;
	w_ext_trig <= i_ext_trig AND (NOT r_ext_trig);
	process(i_sys_rst,i_sys_clk)	
		begin
			if (i_sys_rst = '1') then	
				r_compare_set_value <= x"00";         --
			elsif (i_sys_clk'event AND i_sys_clk = '1') then	
				if (w_ext_trig = '1') then
					case r_compare_set_value is
					when x"00" => r_compare_set_value <= x"0a";
					when x"0a" => r_compare_set_value <= x"14";
					when x"14" => r_compare_set_value <= x"1e";
					when x"1e" => r_compare_set_value <= x"28";
					when x"28" => r_compare_set_value <= x"32";
					when x"32" => r_compare_set_value <= x"3c";
					when x"3c" => r_compare_set_value <= x"46";
					when x"46" => r_compare_set_value <= x"50";
					when x"50" => r_compare_set_value <= x"5a";
					when x"5a" => r_compare_set_value <= x"00";
					when others => r_compare_set_value <= x"00";
				end case;
				end if;
			end if;
	end process;
	o_compare_set_value <= r_compare_set_value;
end architecture behavior;
